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ICS651-03
VOIP Clock Source
Description
The ICS651-03 is a low cost frequency generator designed to support voice-over-internet protocol (VOIP) applications. Using analog/digital Phase-Locked Loop (PLL) techniques, the device uses a standard fundamental mode, inexpensive crystal input to produce four output clocks supporting DSP, video encoder, and memory functions. To form a complete VOIP clocking solution use the ICS651-02 companion device. The device also has a power down feature that tri-states the clock outputs and turns off the PLL when the PDTS pin is taken low.
Features
* * * * * * * * * *
Packaged in 16-pin TSSOP Replaces multiple crystals and oscillators Input crystal or clock frequency of 27 MHz Fixed reference output frequency of 80 MHz Fixed output frequency of 48 MHz Fixed output frequency of 25 MHz Reference output frequency of 27 MHz Duty cycle of 40/60 Operating voltage of 3.3 V Advanced, low power CMOS process
Block Diagram
VDD 6
PLL1
80M
PLL2
48M
25M 27 MHz crystal input X1 Crystal Oscillator/ Clock Buffer REF
X2
External capacitors may be required.
3 GND PDTS
(all outputs and PLLs)
MDS 651-03 A Integrated Circuit Systems
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525 Ra ce St reet, Sa n Jose, C A 9 5126
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ICS651-03 VOIP Clock Source
Pin Assignment
X1 GND PDTS 25M GND VDD VDD 48M 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 X2 VDD REF VDD VDD VDD GND 80M
16-pin (173 mil) TSSOP
Pin Descriptions
Pin Number
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Pin Name
X1 GND PDTS 25M GND VDD VDD 48M 80M GND VDD VDD VDD REF VDD X2
Pin Type
Input Power Input Output Power Power Power Output Output Power Power Power Power Output Power Output Connect to ground.
Pin Description
Crystal connection. Connect to 27 MHz crystal input. Powers down entire chip and tri-states outputs when low. Internal pull-up resistor. 25 MHz clock output. Weak internal pull-down when tri-state. Connect to ground. Connect to +3.3 V. Connect to +3.3 V. 48 MHz clock output. Weak internal pull down when tri-state. 80 MHz clock output. Weak internal pull down when tri-state. Connect to ground. Connect to +3.3 V. Connect to +3.3 V. Connect to +3.3 V. Reference 27 MHz output. Weak internal pull-down when tri-state. Connect to +3.3 V. Crystal connection. Connect to 27 MHz crystal input.
MDS 651-03 A In te grated Circu it Syste m s
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52 5 Race Stre et, San Jose, CA 9512 6
Revision 112603 te l (4 08) 297 -1201 w w w. i c s t . c o m
ICS651-03 VOIP Clock Source
External Components
Decoupling Capacitor
As with any high performance mixed-signal IC, the ICS651-03 must be isolated from system power supply noise to perform optimally. A decoupling capacitor of 0.01F must be connected between each VDD and the PCB ground plane.
PCB Layout Recommendations
For optimum device performance and lowest output phase noise, the following guidelines should be observed. 1) The 0.01F decoupling capacitors should be mounted on the component side of the board as close to the VDD pin as possible. No vias should be used between the decoupling capacitors and VDD pins. The PCB trace to VDD pins should be kept as short as possible, as should the PCB trace to the ground via. 2) The external crystal should be mounted just next to the device with short traces. The X1 and X2 traces should not be routed next to each other with minimum spaces, instead they should be separated and away from other traces. 3) Place the 33 series termination resistor (if needed) close to the clock output to minimize EMI. 4) An optimum layout is one with all components on the same side of the board, minimizing vias through other signal layers. Other signal traces should be routed away from the ICS651-03. This includes signal traces just underneath the device, or on layers adjacent to the ground plane layer used by the device.
Series Termination Resistor
Clock output traces over one inch should use series termination. To series terminate a 50 trace (a commonly used trace impedance), place a 33 resistor in series with the clock line, as close to the clock output pin as possible. The nominal impedance of the clock output is 20.
Crystal Load Capacitors
The device crystal connections should include pads for small capacitors from X1 to ground and from X2 to ground. These capacitors are used to adjust the stray capacitance of the board to match the nominally required crystal load capacitance. Because load capacitance can only be increased in this trimming process, it is important to keep stray capacitance to a minimum by using very short PCB traces (and no vias) between the crystal and device. Crystal capacitors must be connected from each of the pins X1 and X2 to ground. The value (in pF) of these crystal caps should equal (CL -6 pF)*2. In this equation, CL= crystal load capacitance in pF. Example: For a crystal with a 16 pF load capacitance, each crystal capacitor would be 20 pF [(16-6) x 2] = 20.
MDS 651-03 A In te grated Circu it Syste m s
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52 5 Race Stre et, San Jose, CA 9512 6
Revision 112603 te l (4 08) 297 -1201 w w w. i c s t . c o m
ICS651-03 VOIP Clock Source
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS651-03. These ratings, which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range.
Item
Supply Voltage, VDD All Inputs and Outputs Ambient Operating Temperature Storage Temperature Junction Temperature Soldering Temperature -0.5 V to 7 V
Rating
-0.5 V to VDD+0.5 V 0 to +70C -65 to +150C 175C 260C
Recommended Operation Conditions
Parameter
Ambient Operating Temperature Power Supply Voltage (measured in respect to GND)
Min.
0 +3.135
Typ.
+3.3
Max.
+70 +3.465
Units
C V
DC Electrical Characteristics
Unless stated otherwise, VDD = 3.3V 5%, Ambient Temperature 0 to +70C
Parameter
Operating Voltage Supply Current Power Down Current Input High Voltage Input Low Voltage Output High Voltage Output High Voltage Output Low Voltage Short Circuit Current Input Capacitance, inputs
Symbol
VDD IDD IDDPD VIH VIL VOH VOH VOL IOS CIN
Conditions
No load, PDTS=1 No load, PDTS=0 PDTS PDTS IOH = -4 mA IOH = -12 mA IOL = 12 mA Clock outputs
Min.
3.135
Typ.
3.3 21 90
Max.
3.465
Units
V mA A V
2 0.8 VDD-0.4 2.4 0.4 70 5
V V V V mA pF
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52 5 Race Stre et, San Jose, CA 9512 6
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ICS651-03 VOIP Clock Source
Parameter
Nominal Output Impedance Internal pull-up resistor Internal pull-down resistor
Symbol
ZOUT RPU RPD
Conditions
PDTS pins
Min.
Typ.
20 700 200
Max.
Units
k k
AC Electrical Characteristics
Unless stated otherwise, VDD = 3.3V 5%, Ambient Temperature 0 to +70C
Parameter
Input Frequency Output Rise Time Output Fall Time Output Clock Duty Cycle Absolute Clock Period Jitter Frequency synthesis error Output Enable Time Output Disable Time
Symbol
fIN tOR tOF
Conditions
20% to 80% (Note 1) 80% to 20% (Note 1) at VDD/2 (Note 1) (Note 1)
Min.
Typ.
27 1.0 1.0
Max. Units
MHz ns ns 60 % ps ppm s ns
40 100 0 250 20
tOE tOD
PDTS high to output locked to 1% PDTS low to tri-state
Note 1: Measured with a 15 pF load.
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52 5 Race Stre et, San Jose, CA 9512 6
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ICS651-03 VOIP Clock Source
Thermal Characteristics
Parameter
Thermal Resistance Junction to Ambient
Symbol
JA JA JA JC
Conditions
Still air 1 m/s air flow 3 m/s air flow
Min.
Typ.
78 70 68 37
Max. Units
C/W C/W C/W C/W
Thermal Resistance Junction to Case
Marking Diagram
16 9
651G-03 ###### YYWW$$
1
Notes: 1. ###### is the lot code. 2. YYWW is the last two digits of the year, and the week number that the part was assembled.
8
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52 5 Race Stre et, San Jose, CA 9512 6
Revision 112603 te l (4 08) 297 -1201 w w w. i c s t . c o m
ICS651-03 VOIP Clock Source
Package Outline and Package Dimensions (16-pin TSSOP, 173 Mil. Narrow Body)
Package dimensions are kept current with JEDEC Publication No. 95
Millimeters Symbol Min Max Inches Min Max
16
E1 IN D EX AR EA
E
1
2
D
A A1 A2 b C D E E1 e L aaa
-1.20 0.05 0.15 0.80 1.05 0.19 0.30 0.09 0.20 4.90 5.1 6.40 BASIC 4.30 4.50 0.65 Basic 0.45 0.75 0 8 -0.10
-0.047 0.002 0.006 0.032 0.041 0.007 0.012 0.0035 0.008 0.193 0.201 0.252 BASIC 0.169 0.177 0.0256 Basic 0.018 0.030 0 8 -0.004
A 2 A 1
A
c
-Ce
b S E A T IN G P LA N E L
aaa C
Ordering Information
Part / Order Number
ICS651G-03 ICS651G-03T
Marking (both)
(see gage 6)
Shipping packaging
Tubes Tape and Reel
Package
16-pin TSSOP 16-pin TSSOP
Temperature
0 to +70 C 0 to +70 C
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments.
MDS 651-03 A In te grated Circu it Syste m s
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52 5 Race Stre et, San Jose, CA 9512 6
Revision 112603 te l (4 08) 297 -1201 w w w. i c s t . c o m

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